I2C Protocol Subtleties – Part 1

This posting is the initially in a collection describing the much more ‘subtle’ factors of the I2C Protocol, originally formulated by Philips.

Since you happen to be examining this sequence, I am assuming you currently know what the I2C bus is, and you are searching to stay clear of some suffering when you need to have to use it in a challenge. If so, you have appear to the proper location. If not, I will be adding some introductory I2C data soon at my web page.

Just so we are distinct, this collection will not involve protection of the Large-speed manner, as this is significantly distinctive from the design and actions of the standard 2-wire shared-bus implementation, and is also not that commonly applied. You can find lots of fantastic reference product readily available on the Web that addresses this manner.

This is a quick checklist of what will be covered in the rest of the series:

• lacking Start off
• missing Halt
• Recurring Start out
• missing facts bits
• missing ACK/NAK
• details after NAK
• again-to-again mistakes
• pullup resistors
• bus repeaters
• implementation employing a total-hardware TWI or I2C peripheral
• implementation applying a USI peripheral
• implementation utilizing a USART peripheral
• SMBus distinctions from I2C

Now, on to the good stuff!

For this write-up, we will concentrate on the 3 types of implementations you can expect to locate in styles currently: full hardware, components/program blend, and comprehensive software package (or ‘bit-bang’ as it is in some cases termed).

Quite a few microcontrollers right now, even some minimal-finish gadgets, contain a totally-components I2C peripheral. Atmel refers to theirs as TWI, Microchip phone calls theirs I2C other suppliers use very similar naming. When employing a thoroughly-components method, it is actually complicated to make any kind of bus error unless of course you misunderstand how the peripheral performs or what a proper I2C bus sequence ought to glance like. In normal, while, this method involves the the very least in-depth knowledge of the protocol by itself.

The USI peripheral observed in some Atmel devices is a small-components style and design that depends on computer software interaction to make it a finish implementation. This multipurpose peripheral can essentially be utilized for I2C, SPI and UART configurations, and is appropriate for lower-conclusion products the place adding all 3 peripherals would be price-prohibitive. Although it involves much more coding than a TWI or total-hardware I2C peripheral, it is in some ways a lot more versatile. This strategy requres a more in-depth comprehending of the protocol, as you are responsible for shifting from one particular point out to the following, and it is achievable to go in the completely wrong route.

And lastly, applying a 100% application approach needs a whole being familiar with of the I2C protocol. Just about each individual microcontroller seller gives software notes and code illustrations for making an I2C Master product using a pure-software answer. Compared with a UART, I2C is a clocked (instead than timed) protocol, so interruptions in the execution of the protocol are tolerated properly, allowing for interrupts to be serviced without the need of worry for dropping facts. The optimum velocity of the computer software-based mostly resolution is in the long run established by the CPU clock speed, and typically a Grasp implementation can conveniently attain the 400KHz price.

A computer software-dependent implementation of a Slave unit is significantly more demanding. Without having components assistance, the software package will have to watch the two the SDA and the SCL traces concurrently in purchase to detect clock edges and know positively the state of the SDA line prior to the increase or drop of SCL. Detection of a Get started or Cease ailment will commonly demand the use of interrupts, normally the software package would want to be 100% consumed with checking SCL and SDA. Software package-dependent Slave implementations have a tendency to be CPU-sure, requiring many MIPS to reach even 100KHz operation. As a result, accurate software program-only Slave implementations may perhaps not even exist for some microcontroller households, and others might not be able of reaching comprehensive 100KHz bus speed.

With this hardware and application foundation having been laid, we will dive deeper into the protocol by itself in our following short article. Many thanks for reading!

(Copyright 2010 Robert G. Fries)